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Re: P4 and on Memory Mapping
On Wed, 5 Jan 2000, Ross Myers wrote:
> Hi all,
>
> On and off I've been working through a 16176424 Memcal, I've got some
> questions on the A/D Converter in GM's 68pin HC11 type CPU, this CPU is
> numbered 16127475.
> Here's what I've found -
>
> The Motorola HC11F1 book states that the A/D registers are at -
> $1030 (ADCTL)
> $1031 (ADR1)
> $1032 (ADR2)
> $1033 (ADR3)
> $1034 (ADR4)
> $1039 (OPTION)
>
> >From my disassembly of a '424' Memcal these match O.K but they are mapped
> from $30xx, so the ADR's are at $3031 - $3034.
> Is this a Remap of the system or is that where GM requests these to be put
> in their CPU's?.
>
If you write to the correct setup register you can put the ADR in a
wide varitey of places.
> That being the case how comparable are the rest of the registers?, Port
> locations?.
>
> NEXT PROBLEM -
>
> When an A/D conversion is requested in this PCM it does 4 channels at a
> time, but before it does it jumps to the following two routines, I think
> they are setting up which channels to read (0-3) or (4-7). Please assembly
> guru's help me out here.
> Hope it all lines up -
> -----------------------------------------
>
> ldx #0x3000 ;A/D or CPU location?
>
Generic addres of the base of the registers. GM seems to like to use
this so they can use th ldaa 0x33,x type offsets. They don't always
do it this way, but the do quite a bit.
It may save one byte of operand code in each of the ldaa instructions
since an offset request 1 byte and a address requires 2.
Routine1 looks like a setup routine,but I don't know what it is doing.
0x1038 on mine is a weird option register.
The 0x10 in the second routine
selects which a/d convertors. 0x10 selects the first 4 and 0x14 would
select teh second set of 4. The first bit of the lower nibble needs
to be zero (0x08 needs to be clear), and the lower two bits (0x03)
don't matter.
Routine2 is wait until conversion is coplete. The format of 0x1030
is:
0x1030 ADCTL - A/D Control/Status
0x80 CCF - Conversion Complete Flag
1 = Conversion Complete
0x40 Always 0
0x20 SCAN - Continuous Scan Control
1 = Continuously update A/D values
0x10 MULT - Multiple Channel/Single Channel Control
0 = Perform 4 conversion on a single channel
1 = Put 4 channels into each of the 4 registers
Lower Nibble - Defines channel selection
0000 - 0111 = Defines channel #0 through #7
1000 - 1011 = Reserved
1100 - 1111 = Refrence voltages
So the value being written to 30030 sets ultiple and starts the
conversion. The rest is really give it enough time to complete the
converstion. Basically check the conversion complete bit, but only do
it up to 13 times before givving up. This is also done alot in the
one I have, they usually set an error code if they hit 13 without the
conversion complete.
sei ;Disable Interupts >
> ldaa #0x07 ;??
> jsr Routine1 ;?? Shown Below
>
> ldaa #0x10 ;??
> jsr Routine2 ;?? Shown Below
>
> ldaa 0x31,x ;A/D ADR1 - $3031
> staa IATA2D ;Store A/D IAT Value
> ldaa 0x32,x ;A/D ADR2 - $3032
> staa CTSA2D ;Store A/D CTS Value
> ldaa 0x33,x ;A/D ADR3 - $3033
> staa TTSA2D ;Store A/D TTS Value
> ldaa 0x34,x ;A/D ADR4 - $3034
> staa BATA2D ;Store A/D Batt Voltage
>
> cli ;Re-enable interrupts
>
> **************************************
> Routine1:
> bclr 0x08,x,#0x38
> lsla
> lsla
> lsla
> oraa 0x08,x
> staa 0x08,x
> rts
>
> **************************************
> Routine2:
> staa ADCTL ;Store at A/D Control
> ldab #0x0C
> LAB1: brset 0x30,x,#0x80,LAB2
> decb
> bne LAB1
> LAB2: rts
>
> ***************************************
>
>
> And lastly, we refer to the 68HC11 based ECM/PCM's as P4's right, however
> what I don't get is the 808/165 etc use a 52pin CPU, whereas alot of the
> later ECM/PCM's use a 68pin, different CPU's right, why the same Px
> designation then?
>
> I've been out working in the garden all day, had too much time to think
> about all this stuff :-)
>
> Thanks,
> Ross Myers
>
>
>
>
>