Re: 747 Rom Emulator / design

[steve ravet <sravet@arm.com>]

rr wrote:
> 
> Dual port ram is really not required. It's expensive and can be
> tough to get. Remember that the ecm's bus cycle time is almost
> a usec. Some 100 to 150 nsec SRAM can easily be updated
> within a part of the cycle.

But the PIC that generates address/data/cs, even at 20 MHz, can't
generate a complete write cycle between ECM read cycles.  Ludis posted
when this first topic came up how often the ECM typically reads the PROM
and there was no way to squeeze writes in between them.  At least not
with a PIC.  a PLD or something like that could probably buffer a write
from the PIC, and squirt it in when the ECM isn't trying to read.

> 
> Another way to look at it is: Does it matter if the ecm goes into
> limp when your updating the ram, you can't be driving at
> the same time your punching keys on a laptop.

Agreed.  The current design is fine in that respect.  But, if you want
to update without killing the engine, then AFAIK either a DP ram, or
separate banks that are switched with muxes, or maybe a fast pld/fpga
that can write between reads is required, and of the three I think the
DP ram is the "best" solution.

> 
> BobR.
> 
> <snip>
> 

--steve

-- 
Steve Ravet
steve.ravet@arm.com
ARM,Inc.
www.arm.com
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