Here is a good description.

This is used to offload some of the processing from the main processor to other chips on the circuit board. SPI is used for things that are slow. It will require at least 8 clock cycles to get data rather than the one??? to load from a chip on the address bus.

= Assembly Details =

Can someone fill in how you go about reading from an SPI connected chip?

Put data to be sent over the SPI bus in the SPI Data Register at $4000.

Select SPI chip to send/receive from using I/O port select register at $4002.

Set SPI Status Register bit 7 to zero to start the transmission.

The data will be returned in the SPI Data Register at $4000.

I think you need to futz with the MCU Status & Control Register at $3FFC to make this happen. This is mostly from memory, so some details might be missing or incorrect.

= Hardware Details =

On a GM ECM, the processor is the MASTER and the extra chips are the SLAVEs

It uses at minimum 4 lines:

*Chip Select (~CS): You will see this called CS or ~CS or /CS or *CS or CSn, etc to indicate that this is negative logic. Basically, when the voltage on the line is 0, this chip has been selected. When the voltage is high (in our case 5V) the chip is not selected. This is known as "active low". Sometimes called CE for Chip Enable. Some chips reverse this logic (1 is CS, 0 is off).

*SDO: This is the serial data output line. The signal is called MOSI for Master Out, Slave In

*SDI: This is the serial data input line. The signal is called MISO for Master In, Slave Out.

*SCLK: This is a clock signal. Every time a new bit goes out on the data line, it pulses the voltage to tell the chip that there is valid data on the line. At the same time, the chip is reading

Every chip on the SPI bus will have it's own CS line. They all share the SDI, SDO, and SCLK lines, but only listen when they have been selected.

-- AlexHarford - 30 Jun 2006